COMP4DRONES - User contributions [en]

System integration and verification

2022-10-03T15:22:46Z

Uniss:

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-16]]
|MDC
|UNISS
|Formal verification suite working at model level
|}

System Design

2022-10-03T15:22:34Z

Uniss:

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-16]]
|MDC
|UNISS
|Formal verification suite working at model level
|}

System Requirements Analysis

2022-10-03T15:22:22Z

Uniss:

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-06]]
|Modelling & Simulation Tool
|BUT
|
|-
|[[WP6-07]]
|Mission design and optimization
|BUT
|
|-
|[[WP6-24]]
|Papyrus for Robotics
|CEA
|
|-
|[[WP6-25]]
|S3D
|UNICAN
|
|-
|[[WP6-01]]
|Workflow engine
|AIT
|
|-
|
|Testing Tool Set
|
|
|-
|
|Paparazzi UAV
|
|
|-
|
|AirMPL
|
|
|-
|[[WP6-16]]
|SAGE Verification Suite
|UNISS
|Formal verification suite working at model level
|-
|
|Sherpa drone simulator
|
|
|-
|
|Big Data Analytics Tool
|
|
|-
|
|Simcenter Amesim
|
|
|-
|
|SoSIM
|
|
|-
|
|SABT
|
|
|-
|
|e-Handbook
|
|
|}

HW analysis and Design

2022-10-03T15:21:45Z

Uniss:

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-15]]
|MDC
|UNISS
|Multi-Dataflow Composer for reconfigurable HW accelerators
|}

HW development

2022-10-03T15:17:23Z

Uniss:

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-15]]
|MDC
|UNISS
|Multi-Dataflow Composer for reconfigurable HW accelerators
|}

System Requirements Analysis

2022-10-03T15:17:12Z

Uniss:

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-06]]
|Modelling & Simulation Tool
|BUT
|
|-
|[[WP6-07]]
|Mission design and optimization
|BUT
|
|-
|[[WP6-24]]
|Papyrus for Robotics
|CEA
|
|-
|[[WP6-25]]
|S3D
|UNICAN
|
|-
|[[WP6-01]]
|Workflow engine
|AIT
|
|-
|
|Testing Tool Set
|
|
|-
|
|Paparazzi UAV
|
|
|-
|
|AirMPL
|
|
|-
|[[WP6-16]]
|SAGE Verification Suite
|UNISS
|Multi-Dataflow Composer for reconfigurable HW accelerators
|-
|
|Sherpa drone simulator
|
|
|-
|
|Big Data Analytics Tool
|
|
|-
|
|Simcenter Amesim
|
|
|-
|
|SoSIM
|
|
|-
|
|SABT
|
|
|-
|
|e-Handbook
|
|
|}

System integration and verification

2022-10-03T15:15:05Z

Uniss: Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-16 |MDC |UNISS | |}"

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-16]]
|MDC
|UNISS
|
|}

System Design

2022-10-03T15:14:50Z

Uniss: Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-16 |MDC |UNISS | |}"

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-16]]
|MDC
|UNISS
|
|}

System Requirements Analysis

2022-10-03T15:14:18Z

Uniss:

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-06]]
|Modelling & Simulation Tool
|BUT
|
|-
|[[WP6-07]]
|Mission design and optimization
|BUT
|
|-
|[[WP6-24]]
|Papyrus for Robotics
|CEA
|
|-
|[[WP6-25]]
|S3D
|UNICAN
|
|-
|[[WP6-01]]
|Workflow engine
|AIT
|
|-
|
|Testing Tool Set
|
|
|-
|
|Paparazzi UAV
|
|
|-
|
|AirMPL
|
|
|-
|[[WP6-16]]
|SAGE Verification Suite
|UNISS
|
|-
|
|Sherpa drone simulator
|
|
|-
|
|Big Data Analytics Tool
|
|
|-
|
|Simcenter Amesim
|
|
|-
|
|SoSIM
|
|
|-
|
|SABT
|
|
|-
|
|e-Handbook
|
|
|}

WP6-16

2022-10-03T15:13:39Z

Uniss: Created page with "= SAGE = {|class="wikitable" | ID|| WP6-SAGE |- | Contributor || UNISS |- | Levels || Tool |- | TRL || 3 |} == Detailed Description == The tools in the SAGE Verification Suite (SAGE-VS) proposed by UNISS to address UC5 targets targets requirement consistency checking (ReqV), automatic test pattern generation (ReqT) and Neural Network verification (NeVer). ==Contribution and Improvements== *ReqV: **Formulate the technical requirements/specification using Proper..."

= SAGE =
{|class="wikitable"
| ID|| WP6-SAGE
|-
| Contributor || UNISS
|-
| Levels || Tool
|-
| TRL || 3
|}

== Detailed Description ==

The tools in the SAGE Verification Suite (SAGE-VS) proposed by UNISS to address UC5 targets targets requirement consistency checking (ReqV), automatic test pattern generation (ReqT) and Neural Network verification (NeVer).

==Contribution and Improvements==
*ReqV:
**Formulate the technical requirements/specification using Property Specification Patterns (PSP), manually or using the wizard offered by the tool.
**Verify the consistency.
**Examine the feedback returned by the tool in the case of inconsistencies.
*ReqT:
**Load the technical requirements/specification (in PSP) and the code related to the System Under Test.
**Generate the test suite.
*Never:
**Design and train a DNN in pyTorch or load a DNN in ONNX format
**Encode the property to verify
**Launch the verification process

==Current Status==

MDC has been tested in the context of UC5-D1 to model the application that needs to be accelerated on an FPGA so as to meet real-time responses: an AES encryption/decryption block provided by RO Technologies. It has successfully achieved a performance improvement of 2x.

==Example of use==

In the following we present an example related to NeVer.
From Scenario 5.1.3 described in D1.1, Uncle John, as a wise farmer, knows that it would be good to save also a bit of his own effort without losing money in hiring someone to do the treatments. Therefore, he buys a rover that under the lead of its master (the image acquisition drone) actuates the treatment as determined in the acquisition campaign. This improvement results into:
a. The possibility of saving Uncle John precious time and effort.
b. The possibility of promptly intervening on nutritional deficiencies, other disease or insect infestations to avoid their worsening/spreading.
In this context, the acquisition/monitoring system should be able to recognize nutritional deficiencies or other diseases by processing input images and the correctness of the classification is of paramount importance. Considering a Deep Neural Network (DNN) trained to deal with the classification task, it is well-established the sensitivity to adversarial perturbations -- i.e., minimal changes to correctly classified input data that cause a network to respond in unexpected and incorrect ways – of this kind of technology, so the need for tools to analyse (and possibly repair) DNNs is strong.

==Evaluation==

The ReqV and ReqT tools have been evaluated in collaboration with Abinsula, that provided their internal templates for the Requirements Traceability Matrix and Validation Test, continuously providing support in identifying the requirements classifications and in the application of their internal procedures.
The tools have been evaluated in the context of a real use case which is currently under production in Abinsula. The use case count almost two hundred requirements, related to customer requirements, applicable standards, hardware provided by the customer, and technical assumption.
For NDA reasons details about the use case cannot be provided, however results demonstrated that the ReqV and ReqT are efficient in verifying the requirements consistency and generating the test suite, saving effort.
This collaboration is going to be carried on further in the context of other AIDOaRt European Project, to develop procedures, based on the application of formal methods and AI/ML techniques, to enhance the automated verification of systems applied in real safety critical applications.

HW development

2022-10-03T15:08:07Z

Uniss: Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-15 |MDC |UNISS | |}"

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-15]]
|MDC
|UNISS
|
|}

HW analysis and Design

2022-10-03T15:07:38Z

Uniss:

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-15]]
|MDC
|UNISS
|
|}

HW analysis and Design

2022-10-03T15:04:55Z

Uniss: Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-13 |MDC |UNISS | |}"

{| class="wikitable"
|ID
|Tool name
|Tool provider
|Short description
|-
|[[WP6-13]]
|MDC
|UNISS
|
|}

WP6-15

2022-10-03T15:02:49Z

Uniss: /* Multi-Dataflow Composer */

= Multi-Dataflow Composer =
{|class="wikitable"
| ID|| WP6-MDC
|-
| Contributor || UNISS
|-
| Levels || Tool
|-
| Require || Application definition and FPGA-based System-on-Chip
|-
| Provide || Ready-to-use reconfigurable HW accelerator
|-
| Input ||
* Dataflow application specification(s)
* HDL actor definition(s)
* Communication protocol
* Target architecture
|-
| Output ||
* Multi-dataflow network
* Coarse-grained reconfigurable accelerator RTL
* Co-processor RTL
* Programming tables
|-
| C4D tooling || n.a.
|-
| TRL || 5/6
|-
| License || Open-source
|}

== Detailed Description ==

Although FPGA technology has the potential to satisfy the many performances, energy and predictability requirements of drone systems and applications, FPGA development is notoriously a complex task.

To deal with this problematic, the baseline feature of this component revolves around the composition of coarse-grained reconfigurable HW accelerators (CGRA) starting from a set of dataflow applications. The baseline feature involves two main components:

* '''Multi-Dataflow Generator (MDG)''': it merges together different dataflows into one unique reconfigurable multi-dataflow by the insertion of switching modules. Currently, two merging algorithms are supported: empiric and Moreano. The former is more suitable for non-recursive dataflows but less optimized than the latter.
* '''Platform composer (PC)''': it derives the RTL description of the CGRA from the multi-dataflow. It requires the user to define the communication protocol between actors in hardware (XML) and the RTL description of the actors involved in the dataflows (HDL Components Library, HCL).
This component also provides an automatic coprocessor generation, which automatically embeds the generated CGRA into a ready-to-use Xilinx IP. The user can choose among different options:

* '''Processor''': soft-core (Microblaze) or hardcore (ARM)
* '''Processor-Coprocessor coupling''': Memory-mapped or FIFO-based
* '''Direct Access Memory Module''': enable or not the usage of DMA

==Contribution and Improvements==
Regarding the contribution associated to C4D, this component will be extended to be able to automatically generate plug-and-play coarse-grained reconfigurable HW accelerators that can be used by WP6-13 component.

In the specific case of UC5-D1, the MDC tool is used to model the application that needs to be accelerated on an FPGA so as to meet real-time responses: an AES encryption/decryption block provided by RO Technologies. To do so, the application is divided in sub-blocks (called actors) that will be automatically interconnected thanks to the code generation capabilities of the tool. Each of these actors have been implemented in Verilog/SystemVerilog. Additionally, since the tool automatically connects the actors using First-In-First-Out (FIFO) blocks (already available in the tool repository), pipelining is transparently and automatically enabled within the accelerator.

== Interoperability with other C4D tools ==

MDC has been extended with a new backend compatible with the OODK tool (Component WP6-13), where a wrapper surrounding the accelerator is generated, enabling a direct connection from MDC to OODK.
[[File:MDC_interoperability_graph.png|300px|thumb|frame|center| MDC interoperability graph]]

==Current Status==

MDC has been tested in the context of UC5-D1 to model the application that needs to be accelerated on an FPGA so as to meet real-time responses: an AES encryption/decryption block provided by RO Technologies. It has successfully achieved a performance improvement of 2x.

==Design and Implementation==

Considering the specific context of C4D, the tool output is directly connected to the OODK toolchain. Consequently, the design and implementation flow works as follows:

* Define the three inputs that are required:
** Implement the task(s) to be accelerated using a dataflow approach.
** Define the HDL version of the actors composing the tasks (manually or with HLS tools).
** Define the communication protocol to be used inside and outside the accelerator.
* Using the MDG functionality, if more than one task has been specified, merge the tasks to be accelerated into a reconfigurable multi-dataflow.
* Depending on the target architecture, the user must select the files to be generated, that could include the accelerator RTL description and a wrapping logic surrounding the accelerator itself that could allow the user to 1) use the coarse-grained reconfigurable accelerator as a co-processor or 2) to plug the accelerator with an FPGA overlay, as in the case of this project.
* Run the automatically generated scripts to port the code to Vivado.
* Synthesize and implement it on the target FPGA device.

File:MDC interoperability graph.png

2022-10-03T15:02:25Z

Uniss:

WP6-15

2022-10-03T15:00:09Z

Uniss: /* Multi-Dataflow Composer */

= Multi-Dataflow Composer =
{|class="wikitable"
| ID|| WP6-MDC
|-
| Contributor || UNISS
|-
| Levels || Tool
|-
| Require || Application definition and FPGA-based System-on-Chip
|-
| Provide || Ready-to-use reconfigurable HW accelerator
|-
| Input ||
* Dataflow application specification(s)
* HDL actor definition(s)
* Communication protocol
* Target architecture
|-
| Output ||
* Multi-dataflow network
* Coarse-grained reconfigurable accelerator RTL
* Co-processor RTL
* Programming tables
|-
| C4D tooling || n.a.
|-
| TRL || 5/6
|-
| License || Open-source
|}

== Detailed Description ==

Although FPGA technology has the potential to satisfy the many performances, energy and predictability requirements of drone systems and applications, FPGA development is notoriously a complex task.

To deal with this problematic, the baseline feature of this component revolves around the composition of coarse-grained reconfigurable HW accelerators (CGRA) starting from a set of dataflow applications. The baseline feature involves two main components:

* '''Multi-Dataflow Generator (MDG)''': it merges together different dataflows into one unique reconfigurable multi-dataflow by the insertion of switching modules. Currently, two merging algorithms are supported: empiric and Moreano. The former is more suitable for non-recursive dataflows but less optimized than the latter.
* '''Platform composer (PC)''': it derives the RTL description of the CGRA from the multi-dataflow. It requires the user to define the communication protocol between actors in hardware (XML) and the RTL description of the actors involved in the dataflows (HDL Components Library, HCL).
This component also provides an automatic coprocessor generation, which automatically embeds the generated CGRA into a ready-to-use Xilinx IP. The user can choose among different options:

* '''Processor''': soft-core (Microblaze) or hardcore (ARM)
* '''Processor-Coprocessor coupling''': Memory-mapped or FIFO-based
* '''Direct Access Memory Module''': enable or not the usage of DMA

==Contribution and Improvements==
Regarding the contribution associated to C4D, this component will be extended to be able to automatically generate plug-and-play coarse-grained reconfigurable HW accelerators that can be used by WP6-13 component.

In the specific case of UC5-D1, the MDC tool is used to model the application that needs to be accelerated on an FPGA so as to meet real-time responses: an AES encryption/decryption block provided by RO Technologies. To do so, the application is divided in sub-blocks (called actors) that will be automatically interconnected thanks to the code generation capabilities of the tool. Each of these actors have been implemented in Verilog/SystemVerilog. Additionally, since the tool automatically connects the actors using First-In-First-Out (FIFO) blocks (already available in the tool repository), pipelining is transparently and automatically enabled within the accelerator.

== Interoperability with other C4D tools ==

MDC has been extended with a new backend compatible with the OODK tool (Component WP6-13), where a wrapper surrounding the accelerator is generated, enabling a direct connection from MDC to OODK.

==Current Status==

MDC has been tested in the context of UC5-D1 to model the application that needs to be accelerated on an FPGA so as to meet real-time responses: an AES encryption/decryption block provided by RO Technologies. It has successfully achieved a performance improvement of 2x.

==Design and Implementation==

Considering the specific context of C4D, the tool output is directly connected to the OODK toolchain. Consequently, the design and implementation flow works as follows:

* Define the three inputs that are required:
** Implement the task(s) to be accelerated using a dataflow approach.
** Define the HDL version of the actors composing the tasks (manually or with HLS tools).
** Define the communication protocol to be used inside and outside the accelerator.
* Using the MDG functionality, if more than one task has been specified, merge the tasks to be accelerated into a reconfigurable multi-dataflow.
* Depending on the target architecture, the user must select the files to be generated, that could include the accelerator RTL description and a wrapping logic surrounding the accelerator itself that could allow the user to 1) use the coarse-grained reconfigurable accelerator as a co-processor or 2) to plug the accelerator with an FPGA overlay, as in the case of this project.
* Run the automatically generated scripts to port the code to Vivado.
* Synthesize and implement it on the target FPGA device.

WP6-15

2022-10-03T14:59:39Z

Uniss: Created page with "= Multi-Dataflow Composer = {|class="wikitable" | ID|| WP6-MDC |- | Contributor || UNISS |- | Levels || Tool |- | Require || Application definition and FPGA-based System-on-Chip |- | Provide || Ready-to-use reconfigurable HW accelerator |- | Input || | * Dataflow application specification(s) * HDL actor definition(s) * Communication protocol * Target architecture |- | Output || * Multi-dataflow network * Coarse-grained reconfigurable accelerator RTL * Co-p..."

= Multi-Dataflow Composer =
{|class="wikitable"
| ID|| WP6-MDC
|-
| Contributor || UNISS
|-
| Levels || Tool
|-
| Require || Application definition and FPGA-based System-on-Chip
|-
| Provide || Ready-to-use reconfigurable HW accelerator
|-
| Input ||
|
* Dataflow application specification(s)
* HDL actor definition(s)
* Communication protocol
* Target architecture
|-
| Output ||
* Multi-dataflow network
* Coarse-grained reconfigurable accelerator RTL
* Co-processor RTL
* Programming tables
|-
| C4D tooling || n.a.
|-
| TRL || 5/6
|-
| License || Open-source
|}

== Detailed Description ==

Although FPGA technology has the potential to satisfy the many performances, energy and predictability requirements of drone systems and applications, FPGA development is notoriously a complex task.

To deal with this problematic, the baseline feature of this component revolves around the composition of coarse-grained reconfigurable HW accelerators (CGRA) starting from a set of dataflow applications. The baseline feature involves two main components:

* '''Multi-Dataflow Generator (MDG)''': it merges together different dataflows into one unique reconfigurable multi-dataflow by the insertion of switching modules. Currently, two merging algorithms are supported: empiric and Moreano. The former is more suitable for non-recursive dataflows but less optimized than the latter.
* '''Platform composer (PC)''': it derives the RTL description of the CGRA from the multi-dataflow. It requires the user to define the communication protocol between actors in hardware (XML) and the RTL description of the actors involved in the dataflows (HDL Components Library, HCL).
This component also provides an automatic coprocessor generation, which automatically embeds the generated CGRA into a ready-to-use Xilinx IP. The user can choose among different options:

* '''Processor''': soft-core (Microblaze) or hardcore (ARM)
* '''Processor-Coprocessor coupling''': Memory-mapped or FIFO-based
* '''Direct Access Memory Module''': enable or not the usage of DMA

==Contribution and Improvements==
Regarding the contribution associated to C4D, this component will be extended to be able to automatically generate plug-and-play coarse-grained reconfigurable HW accelerators that can be used by WP6-13 component.

In the specific case of UC5-D1, the MDC tool is used to model the application that needs to be accelerated on an FPGA so as to meet real-time responses: an AES encryption/decryption block provided by RO Technologies. To do so, the application is divided in sub-blocks (called actors) that will be automatically interconnected thanks to the code generation capabilities of the tool. Each of these actors have been implemented in Verilog/SystemVerilog. Additionally, since the tool automatically connects the actors using First-In-First-Out (FIFO) blocks (already available in the tool repository), pipelining is transparently and automatically enabled within the accelerator.

== Interoperability with other C4D tools ==

MDC has been extended with a new backend compatible with the OODK tool (Component WP6-13), where a wrapper surrounding the accelerator is generated, enabling a direct connection from MDC to OODK.

==Current Status==

MDC has been tested in the context of UC5-D1 to model the application that needs to be accelerated on an FPGA so as to meet real-time responses: an AES encryption/decryption block provided by RO Technologies. It has successfully achieved a performance improvement of 2x.

==Design and Implementation==

Considering the specific context of C4D, the tool output is directly connected to the OODK toolchain. Consequently, the design and implementation flow works as follows:

* Define the three inputs that are required:
** Implement the task(s) to be accelerated using a dataflow approach.
** Define the HDL version of the actors composing the tasks (manually or with HLS tools).
** Define the communication protocol to be used inside and outside the accelerator.
* Using the MDG functionality, if more than one task has been specified, merge the tasks to be accelerated into a reconfigurable multi-dataflow.
* Depending on the target architecture, the user must select the files to be generated, that could include the accelerator RTL description and a wrapping logic surrounding the accelerator itself that could allow the user to 1) use the coarse-grained reconfigurable accelerator as a co-processor or 2) to plug the accelerator with an FPGA overlay, as in the case of this project.
* Run the automatically generated scripts to port the code to Vivado.
* Synthesize and implement it on the target FPGA device.

WP3-28

2022-10-03T14:58:13Z

Uniss: /* Accelerator Design Methodology for OOCP */

=Accelerator Design Methodology for OOCP=
{|class="wikitable"
| ID|| WP3-28
|-
| Contributor || UNISS
|-
| Levels || System
|-
| Require || Application definition and FPGA-based System-on-Chip
|-
| Provide || Ready-to-use reconfigurable HW accelerator
|-
| Input
|
* Dataflow application specification(s)
* HDL actor definition(s)
* Communication protocol
* Target architecture
|-
| Output
|
* Multi-dataflow network
* Coarse-grained reconfigurable accelerator RTL
* Co-processor RTL
* Programming tables
|-
| C4D building block || The methodology is generic and applicable to generate accelerators for different tasks and scenarios. With respect to C4D, it could POTENTIALLY be used to implement HW accelerators related to perception, actuation, flight-control, payload management or data management.
|-
| TRL || 3 to 4
|}

[[File:wp3-28_01.png|frame|center|Building Block diagram for WP3-28]]

==Detailed Description==

Although FPGA technology has the potential to satisfy the many performances, energy and predictability requirements of drone systems and applications, FPGA development is notoriously a complex task.

To deal with this problematic, the baseline feature of this component revolves around the composition of coarse-grained reconfigurable HW accelerators (CGRA) starting from a set of dataflow applications. The baseline feature involves two main components:

* '''Multi-Dataflow Generator (MDG)''': it merges together different dataflows into one unique reconfigurable multi-dataflow by the insertion of switching modules. Currently, two merging algorithms are supported: empiric and Moreano. The former is more suitable for non-recursive dataflows but less optimized than the latter.
* '''Platform composer (PC)''': it derives the RTL description of the CGRA from the multi-dataflow. It requires the user to define the communication protocol between actors in hardware (XML) and the RTL description of the actors involved in the dataflows (HDL Components Library, HCL).
This component also provides an automatic coprocessor generation, which automatically embeds the generated CGRA into a ready-to-use Xilinx IP. The user can choose among different options:

* '''Processor''': soft-core (Microblaze) or hardcore (ARM)
* '''Processor-Coprocessor coupling''': Memory-mapped or FIFO-based
* '''Direct Access Memory Module''': enable or not the usage of DMA

==Specifications and contribution==
The purpose of this component is to provide a methodology to generate application-specific HW accelerators that can be directly plugged in the final system. Additionally, this component automatically enables coarse-grained reconfiguration capabilities, which enables the capability of having a HW accelerator that can work at different working points (i.e. trade-offs among Quality of Service and Energy consumption) or functionalities (i.e. different implementations related to the same C4D building block).

Regarding the contribution associated to C4D, this component will be extended to be able to automatically generate plug-and-play coarse-grained reconfigurable HW accelerators that can be used by WP3-22 component. To do so, a unified methodology will be provided so as to combine the FPGA overlay provided in WP3-22 with the CGRA generation supported by this component.

==Design and Implementation==
Considering that the HW accelerators that are generated using this component are application specific, the required steps to generate the multi-dataflow networks and its associated CGRA are the following:

* Define the three inputs that are required:
** Implement the task(s) to be accelerated using a dataflow approach.
** Define the HDL version of the actors composing the tasks (manually or with HLS tools).
** Define the communication protocol to be used inside and outside the accelerator.
* Using the MDG functionality, if more than one task has been specified, merge the tasks to be accelerated into a reconfigurable multi-dataflow.
* Depending on the target architecture, the user must select the files to be generated, that could include the accelerator RTL description and a wrapping logic surrounding the accelerator itself that could allow the user to 1) use the coarse-grained reconfigurable accelerator as a co-processor or 2) to plug the accelerator with an FPGA overlay, as in the case of this project.
* Run the automatically generated scripts to port the code to Vivado.
* Synthesize and implement it on the target FPGA device.

WP3-28

2022-10-03T14:38:50Z

Uniss: /* Accelerator Design Methodology for OOCP */

WP3-28

2022-02-25T10:40:10Z

Uniss: Created page with "=Accelerator Design Methodology for OOCP= {|class="wikitable" | ID|| WP3-28 |- | Contributor || UNISS |- | Levels || System |- | Require || Application definition and FPGA-based System-on-Chip |- | Provide || Ready-to-use reconfigurable HW accelerator |- | Input | * Dataflow application specification(s) * HDL actor definition(s) * Communication protocol * Target architecture |- | Input | * Multi-dataflow network * Coarse-grained reconfigurable accelera..."

=Accelerator Design Methodology for OOCP=
{|class="wikitable"
| ID|| WP3-28
|-
| Contributor || UNISS
|-
| Levels || System
|-
| Require || Application definition and FPGA-based System-on-Chip
|-
| Provide || Ready-to-use reconfigurable HW accelerator
|-
| Input
|
* Dataflow application specification(s)
* HDL actor definition(s)
* Communication protocol
* Target architecture
|-
| Input
|
* Multi-dataflow network
* Coarse-grained reconfigurable accelerator RTL
* Co-processor RTL
* Programming tables
|-
| C4D building block || The methodology is generic and applicable to generate accelerators for different tasks and scenarios. With respect to C4D, it could POTENTIALLY be used to implement HW accelerators related to perception, actuation, flight-control, payload management or data management.
|-
| TRL || 3 to 4
|}

[[File:wp3-28_01.png|frame|center|Building Block diagram for WP3-28]]

==Detailed Description==

Although FPGA technology has the potential to satisfy the many performances, energy and predictability requirements of drone systems and applications, FPGA development is notoriously a complex task.

To deal with this problematic, the baseline feature of this component revolves around the composition of coarse-grained reconfigurable HW accelerators (CGRA) starting from a set of dataflow applications. The baseline feature involves two main components:

* '''Multi-Dataflow Generator (MDG)''': it merges together different dataflows into one unique reconfigurable multi-dataflow by the insertion of switching modules. Currently, two merging algorithms are supported: empiric and Moreano. The former is more suitable for non-recursive dataflows but less optimized than the latter.
* '''Platform composer (PC)''': it derives the RTL description of the CGRA from the multi-dataflow. It requires the user to define the communication protocol between actors in hardware (XML) and the RTL description of the actors involved in the dataflows (HDL Components Library, HCL).
This component also provides an automatic coprocessor generation, which automatically embeds the generated CGRA into a ready-to-use Xilinx IP. The user can choose among different options:

* '''Processor''': soft-core (Microblaze) or hardcore (ARM)
* '''Processor-Coprocessor coupling''': Memory-mapped or FIFO-based
* '''Direct Access Memory Module''': enable or not the usage of DMA

==Specifications and contribution==
The purpose of this component is to provide a methodology to generate application-specific HW accelerators that can be directly plugged in the final system. Additionally, this component automatically enables coarse-grained reconfiguration capabilities, which enables the capability of having a HW accelerator that can work at different working points (i.e. trade-offs among Quality of Service and Energy consumption) or functionalities (i.e. different implementations related to the same C4D building block).

Regarding the contribution associated to C4D, this component will be extended to be able to automatically generate plug-and-play coarse-grained reconfigurable HW accelerators that can be used by WP3-22 component. To do so, a unified methodology will be provided so as to combine the FPGA overlay provided in WP3-22 with the CGRA generation supported by this component.

==Design and Implementation==
Considering that the HW accelerators that are generated using this component are application specific, the required steps to generate the multi-dataflow networks and its associated CGRA are the following:

* Define the three inputs that are required:
** Implement the task(s) to be accelerated using a dataflow approach.
** Define the HDL version of the actors composing the tasks (manually or with HLS tools).
** Define the communication protocol to be used inside and outside the accelerator.
* Using the MDG functionality, if more than one task has been specified, merge the tasks to be accelerated into a reconfigurable multi-dataflow.
* Depending on the target architecture, the user must select the files to be generated, that could include the accelerator RTL description and a wrapping logic surrounding the accelerator itself that could allow the user to 1) use the coarse-grained reconfigurable accelerator as a co-processor or 2) to plug the accelerator with an FPGA overlay, as in the case of this project.
* Run the automatically generated scripts to port the code to Vivado.
* Synthesize and implement it on the target FPGA device..

File:Wp3-28 01.png

2022-02-25T10:37:10Z

Uniss:

Main Page

2022-02-25T10:27:04Z

Uniss: Changed title of UNISS component

<strong>Components list</strong>

{| class="wikitable"
|ID
|Contributor
|Title
|-
|[[WP3-01]]
|IKERLAN
|Safety function - Pre-Certified SOM
|-
|[[WP3-02]]
|EDI
|Modular SoC-based embedded reference architecture
|-
|[[WP3-03]]
|BUT
|Sensor information algorithms
|-
|[[WP3-04]]
|HIB
|Computer Vision Components for drones
|-
|[[WP3-10]]
|IFAT
|Component for trusted communication
|-
|[[WP3-13]]
|ENAC
|Paparazzi UAV
|-
|[[WP3-14_1]]
|ENSMA
|Control components that implement potential barriers
|-
|[[WP3-14_2]]
|ENSMA
|Multi-agent swarm control
|-
|[[WP3-15_1]]
|ACORDE
|UWB based indoor positioning
|-
|[[WP3-15_2]]
|ACORDE
|Multi-antenna GNSS/INS based navigation
|-
|[[WP3-16]]
|SCALIAN
|EZ_Chains Fleet Architecture
|-
|[[WP3-19_1]]
|IMEC
|Hyperspectral payload
|-
|[[WP3-19_2]]
|IMEC
|Hyperspectral image processing
|-
|[[WP3-20]]
|MODIS
|Multi-sensor positioning
|-
|[[WP3-22]]
|UNIMORE
|Onboard Compute Platform Desing Methodology
|-
|[[WP3-24]]
|UNIVAQ
|Efficient digital implementation of controllers
|-
|[[WP3-26]]
|UWB
|Droneport: an autonomous drone battery management system
|-
|[[WP3-28]]
|UNISS
|Accelerator Design Methodology for OOCP
|-
|[[WP3-36_1]]
|UDANET
|Smart and predictive energy management system
|-
|[[WP3-36_2]]
|UDANET
|AI drone system modules
|-
|[[WP3-37]]
|Aitek
|Video and data analytics
|-
|[[WP4-2]]
|SCALIAN
|EZ_Land Precision landing
|-
|[[WP4-5]]
|SCALIAN
|AI detection for clearance
|-
|[[WP4-18_A]]
|TEKNE
|Drone-Rover Transponder
|-
|[[WP4-42]]
|SCALIAN
|AI Stabilization
|-
|[[WP5-03]]
|SCALIAN
|EZ_Com Safe fleet communication
|-
|[[WP5-05_A]]
|TEKNE
|LP-WAN for UAV identification and monitoring
|-
|[[WP4-33]]
|UNIVAQ
|Autonomy, cooperation, and awareness
|}

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