WP3-24: Difference between revisions

Revision as of 11:55, 25 March 2022

WP3-24 – Efficient digital implementation of controllers on FPGAs

ID	WP3-24

Contributor	UNIVAQ

Levels	Methodological

Require	FPGAs for the implementation of the proposed control algorithms

Provide	An efficient methodology for the implementation of digital control algorithms on FPGAs based on the pipeline approach.

Input	Control algorithms for the autonomous navigation of drones to be implemented on FPGAs

Output	Lower execution times, and hence smaller sampling times, than its naive implementation. Lower power consumption of the pipelined control algorithm.

C4D building block	Flight Control

TRL	3-4
		
1	Detailed Description

Efficient digital implementation of controllers on FPGAs. In the context of C4D project, the component WP3-24 aims to provide an efficient methodology for the digital implementation of controllers on FPGAs. It is well-known that the use of UAVs in many complex tasks has increased the complexity of the embedded control algorithms that are necessary in order to face more challenging performances, such as: detection and avoiding of obstacles; cooperation among drones; efficient trajectory execution; etc. However, many software solutions also present some limitations, due to its fixed internal architecture. This leads to a full serialization of the data treatment. The more complex is the control and decision algorithm, the longer is its execution time. This, in turn, constitutes a lower bound for the sampling time that can be used in the specific application. Clearly, longer sampling times determine worse controller performances. To obtain higher control performances, one can work in two possible directions. The first is methodological, and consists of designing the control algorithms on the basis of better discrete-time dynamic representations of the vehicle. The second is technological, and regards the use of more performing devices used to implement a given controller. As far as the technological solution is concerned, field-programmable gate arrays (FPGAs) can ensure better performances than software solutions, thanks to the possibility of parallelism and to the increasing integration density, which allows implementing complex control algorithms. In fact, FPGAs are full system-on-chip (SoC) solutions. They allow more flexibility for the implementation of embedded controllers, due to the fact that they include in the same chip various components (processors, memories, hardware multiplier blocks, analog–digital converters, matrix of programmable logic elements-fabric-and buses). The fact that FPGAs integrate both software and hardware resources allow faster implementations of controllers making use of the parallelism. Therefore, FPGAs constitute a valid hardware solution, since it is possible to design an architecture that is customized for the control algorithm to be implemented. This ensures shorter execution times of the algorithm. To further reduce the execution time in FPGAs, some techniques can be used that allow transforming the circuit structure, in order to reduce this time, and possibly the power consumption, maintaining the desired functionality, i.e., implementing the required control input. These (methodological, not technological) techniques include retiming/pipelining, folding/unfolding, interleaving, etc. The proposed methodology for the efficient implementation of controllers on FPGA is focused on retiming and pipelining. The former is a transformation technique used to change the locations of the delay elements in a circuit without affecting the input/output characteristics of the circuit. Pipelining is a special case of retiming used to reduce the critical path, introducing pipelining latches along the data path. Shortening the critical paths, one can increase the clock speed or the sample speed, or one can reduce the power consumption at the same speed.

1.1	Contribution and Improvements

The pipelined implementation technique, here proposed in the context of UAVs control (WP3-24), allows lower execution times, and hence smaller sampling times, than its naive implementation. Moreover, the power consumption of the pipelined control algorithm is lower. These two aspects constitute the main benefits of using a pipelining technique for the implementation of UAV control algorithm on an FPGA. In other words, the main aim behind the component (WP3-24) is to provide an implementation guideline for UAVs control algorithms showing that, when technological solutions such as FPGAs are used, the pipelining methodology can be successfully applied to obtain lower sampling periods, thereby allowing the implementation of more sophisticated controllers for UAVs. The efficiency of the proposed implementation methodology is shown by developing on FPGA a robust sampled—data controller for the autonomous navigation of drone which has been designed in the context of WP4 for C4D project. Finally, through experimental results, it can be shown that the pipelining methodology also allows taking into account the energetic aspects of the controller implementations, and not only the controller performance. This is another very important aspect for onboard systems as in UAVs.