WP6-17: Difference between revisions
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The increasing complexity of nowadays embedded digital systems, especially those based on advanced system-on-chip (SoC) that explicitly use heterogeneous parallel architectures to meet demanding timing performance and power consumption requirements, and their shorter time-to-market are radically changing standard industrial design methodologies. Traditional design approaches based on independent design of HW / SW components are no longer sufficient to efficiently exploit sub-areas of such SoCs. For this reason, system-level HW/SW co-design methods, where designers can early check system-level constraints and evaluate tradeoffs between cost and performance, are becoming increasingly important. These methods are capable of guiding system-level activities using appropriate models, metrics, and tools, and assisting the designer in all those tasks normally entrusted only to his or her experience (e.g., HW / SW architecture definition and system-level HW /SW partitioning ). In this context, this repository presents a reference methodology for electronic system level (ESL) HW/SW co-design, called HEPSYCODE, targeting heterogeneous parallel embedded systems. It has been extended in C4D to meet mixed criticality requirements and to be integrated into UML/MARTE specifications. | |||
== Detailed Description == | == Detailed Description == | ||
TODO | TODO | ||
==Contribution and Improvements== | ==Contribution and Improvements== | ||
Revision as of 17:18, 22 September 2022
HW/SW CO-DEsign of HEterogeneous Parallel dedicated Systems (HEPSYCODE)
| ID | WP6-HEPSYCODE |
| Contributor | UNIVAQ |
| Levels | Tool, Platform |
| Require | Linux, TODO |
| Provide | TODO |
| Input | SystemC models, Platform model, TODO |
| Output | TODO. |
| C4D tooling | n.a. |
| TRL | 4 |
The increasing complexity of nowadays embedded digital systems, especially those based on advanced system-on-chip (SoC) that explicitly use heterogeneous parallel architectures to meet demanding timing performance and power consumption requirements, and their shorter time-to-market are radically changing standard industrial design methodologies. Traditional design approaches based on independent design of HW / SW components are no longer sufficient to efficiently exploit sub-areas of such SoCs. For this reason, system-level HW/SW co-design methods, where designers can early check system-level constraints and evaluate tradeoffs between cost and performance, are becoming increasingly important. These methods are capable of guiding system-level activities using appropriate models, metrics, and tools, and assisting the designer in all those tasks normally entrusted only to his or her experience (e.g., HW / SW architecture definition and system-level HW /SW partitioning ). In this context, this repository presents a reference methodology for electronic system level (ESL) HW/SW co-design, called HEPSYCODE, targeting heterogeneous parallel embedded systems. It has been extended in C4D to meet mixed criticality requirements and to be integrated into UML/MARTE specifications.
Detailed Description
TODO
Contribution and Improvements
Some key aspects of the HEPSYCODE flow for design system improvement are:
- TODO
- TODO
Interoperability with other C4D tools
TODO
Current Status
TODO
Design and Implementation
TODO