User contributions for Uniss
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- 15:22, 3 October 2022 diff hist +48 System integration and verification current
- 15:22, 3 October 2022 diff hist +48 System Design current
- 15:22, 3 October 2022 diff hist −10 System Requirements Analysis current
- 15:21, 3 October 2022 diff hist +58 HW analysis and Design current
- 15:17, 3 October 2022 diff hist +58 HW development current
- 15:17, 3 October 2022 diff hist +58 System Requirements Analysis
- 15:15, 3 October 2022 diff hist +101 N System integration and verification Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-16 |MDC |UNISS | |}"
- 15:14, 3 October 2022 diff hist +101 N System Design Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-16 |MDC |UNISS | |}"
- 15:14, 3 October 2022 diff hist +15 System Requirements Analysis
- 15:13, 3 October 2022 diff hist +3,616 N WP6-16 Created page with "= SAGE = {|class="wikitable" | ID|| WP6-SAGE |- | Contributor || UNISS |- | Levels || Tool |- | TRL || 3 |} == Detailed Description == The tools in the SAGE Verification Suite (SAGE-VS) proposed by UNISS to address UC5 targets targets requirement consistency checking (ReqV), automatic test pattern generation (ReqT) and Neural Network verification (NeVer). ==Contribution and Improvements== *ReqV: **Formulate the technical requirements/specification using Proper..." current
- 15:08, 3 October 2022 diff hist +101 N HW development Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-15 |MDC |UNISS | |}"
- 15:07, 3 October 2022 diff hist 0 HW analysis and Design
- 15:04, 3 October 2022 diff hist +101 N HW analysis and Design Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-13 |MDC |UNISS | |}"
- 15:02, 3 October 2022 diff hist +93 WP6-15 →Multi-Dataflow Composer current
- 15:02, 3 October 2022 diff hist 0 N File:MDC interoperability graph.png current
- 15:00, 3 October 2022 diff hist −2 m WP6-15 →Multi-Dataflow Composer
- 14:59, 3 October 2022 diff hist +4,670 N WP6-15 Created page with "= Multi-Dataflow Composer = {|class="wikitable" | ID|| WP6-MDC |- | Contributor || UNISS |- | Levels || Tool |- | Require || Application definition and FPGA-based System-on-Chip |- | Provide || Ready-to-use reconfigurable HW accelerator |- | Input || | * Dataflow application specification(s) * HDL actor definition(s) * Communication protocol * Target architecture |- | Output || * Multi-dataflow network * Coarse-grained reconfigurable accelerator RTL * Co-p..."
- 14:58, 3 October 2022 diff hist −1 m WP3-28 →Accelerator Design Methodology for OOCP
- 14:38, 3 October 2022 diff hist +1 WP3-28 →Accelerator Design Methodology for OOCP
- 10:40, 25 February 2022 diff hist +4,492 N WP3-28 Created page with "=Accelerator Design Methodology for OOCP= {|class="wikitable" | ID|| WP3-28 |- | Contributor || UNISS |- | Levels || System |- | Require || Application definition and FPGA-based System-on-Chip |- | Provide || Ready-to-use reconfigurable HW accelerator |- | Input | * Dataflow application specification(s) * HDL actor definition(s) * Communication protocol * Target architecture |- | Input | * Multi-dataflow network * Coarse-grained reconfigurable accelera..."
- 10:37, 25 February 2022 diff hist 0 N File:Wp3-28 01.png current
- 10:27, 25 February 2022 diff hist −1 m Main Page Changed title of UNISS component
