User contributions for Uniss

3 October 2022

• 15:2215:22, 3 October 2022 diff hist +48 System integration and verification No edit summary current
• 15:2215:22, 3 October 2022 diff hist +48 System Design No edit summary current
• 15:2215:22, 3 October 2022 diff hist −10 System Requirements Analysis No edit summary current
• 15:2115:21, 3 October 2022 diff hist +58 HW analysis and Design No edit summary current
• 15:1715:17, 3 October 2022 diff hist +58 HW development No edit summary current
• 15:1715:17, 3 October 2022 diff hist +58 System Requirements Analysis No edit summary
• 15:1515:15, 3 October 2022 diff hist +101 N System integration and verification Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-16 |MDC |UNISS | |}"
• 15:1415:14, 3 October 2022 diff hist +101 N System Design Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-16 |MDC |UNISS | |}"
• 15:1415:14, 3 October 2022 diff hist +15 System Requirements Analysis No edit summary
• 15:1315:13, 3 October 2022 diff hist +3,616 N WP6-16 Created page with "= SAGE = {|class="wikitable" | ID|| WP6-SAGE |- | Contributor || UNISS |- | Levels || Tool |- | TRL || 3 |} == Detailed Description == The tools in the SAGE Verification Suite (SAGE-VS) proposed by UNISS to address UC5 targets targets requirement consistency checking (ReqV), automatic test pattern generation (ReqT) and Neural Network verification (NeVer). ==Contribution and Improvements== *ReqV: **Formulate the technical requirements/specification using Proper..." current
• 15:0815:08, 3 October 2022 diff hist +101 N HW development Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-15 |MDC |UNISS | |}"
• 15:0715:07, 3 October 2022 diff hist 0 HW analysis and Design No edit summary
• 15:0415:04, 3 October 2022 diff hist +101 N HW analysis and Design Created page with "{| class="wikitable" |ID |Tool name |Tool provider |Short description |- |WP6-13 |MDC |UNISS | |}"
• 15:0215:02, 3 October 2022 diff hist +93 WP6-15 →Multi-Dataflow Composer current
• 15:0215:02, 3 October 2022 diff hist 0 N File:MDC interoperability graph.png No edit summary current
• 15:0015:00, 3 October 2022 diff hist −2 m WP6-15 →Multi-Dataflow Composer
• 14:5914:59, 3 October 2022 diff hist +4,670 N WP6-15 Created page with "= Multi-Dataflow Composer = {|class="wikitable" | ID|| WP6-MDC |- | Contributor || UNISS |- | Levels || Tool |- | Require || Application definition and FPGA-based System-on-Chip |- | Provide || Ready-to-use reconfigurable HW accelerator |- | Input || | * Dataflow application specification(s) * HDL actor definition(s) * Communication protocol * Target architecture |- | Output || * Multi-dataflow network * Coarse-grained reconfigurable accelerator RTL * Co-p..."
• 14:5814:58, 3 October 2022 diff hist −1 m WP3-28 →Accelerator Design Methodology for OOCP
• 14:3814:38, 3 October 2022 diff hist +1 WP3-28 →Accelerator Design Methodology for OOCP

25 February 2022

• 10:4010:40, 25 February 2022 diff hist +4,492 N WP3-28 Created page with "=Accelerator Design Methodology for OOCP= {|class="wikitable" | ID|| WP3-28 |- | Contributor || UNISS |- | Levels || System |- | Require || Application definition and FPGA-based System-on-Chip |- | Provide || Ready-to-use reconfigurable HW accelerator |- | Input | * Dataflow application specification(s) * HDL actor definition(s) * Communication protocol * Target architecture |- | Input | * Multi-dataflow network * Coarse-grained reconfigurable accelera..."
• 10:3710:37, 25 February 2022 diff hist 0 N File:Wp3-28 01.png No edit summary current
• 10:2710:27, 25 February 2022 diff hist −1 m Main Page Changed title of UNISS component