WP6-13

OODK: Onboard Overlay Development Kit

ID	WP6-13
Contributor	UNIMORE
Levels	Tool
Require	OODK configuration, HW accelerators and FPGA-based System-on-Chip
Provide	Automated deployment of HW accelerators in the companion computer platform
Input	OODK configuration file HW Accelerator RTL designs
Output	OODK system ready to be deployed on FPGA-based System-on-Chip SW stack for offloading computation from the host processor side to the hardware-specific accelerators
C4D tooling	n.a.
TRL	5/6
License	Open-source

Detailed Description

Although FPGA technology can satisfy the performance, energy and predictability requirements of drone systems and applications, FPGA development is a notoriously complex task. This component is a methodology to ease the deployment of application-specific accelerators - or Hardware Processing Units (HWPU) - in the companion computer platform.

It allows for:

• Automated deployment of HW accelerators in the companion computer platform.
• Generation of an application-tailored FPGA overlay. The latter is an HW/SW abstraction layer that integrates and supports HW accelerators and is instantiated in the FPGA-based System-on-Chip.
• SW stack support for streamlined offloading of computation from the host processor side to the hardware-specific accelerators

Target drone application(s) will then run on a Heterogeneous System-on-Chip where:

• Host CPU is an industry-standard, hard-macro multi-core CPU. It executes full-fledged operating systems and other legacy software (e.g., ROS).
• FPGA overlay consists of several clusters grouping a small number of RISC-V-based proxy cores to control the operation of one or more HW accelerators.
• Applications start on the host CPU, and then compute-intensive parts can be offloaded to the FPGA overlay on the programmable logic.
• Target SoC supports interaction with autopilot, ground station, sensor, and/or other I/O.

Contribution and Improvements

OODK is a collection of tools for integrating and configuring HW accelerators (see below UC5-DEM10-DTC-05) and for quickly and effectively offloading computation from the host processor side to the hardware-specific accelerators (see UC5-DEM10-DTC-04).

Figure 80 shows the main functionalities assigned to the OODK. OODK is used to integrate and design the complete system of the FPGA overlay. Thus, it includes an automated flow for the integration and implementation of custom HW accelerators (from MDC and other design methodologies, such as Xilinx Vivado HLS) on our overlay.

Interoperability with other C4D tools

Figure 80 shows the main functionalities assigned to the OODK. OODK is used to integrate and design the complete system of the FPGA overlay.

The original Onboard Overlay Development kit also includes a tool for integrating Xilinx Vivado HLS accelerators into the overlay template. Thanks to the C4D project, the flow for integrating HW Accelerator is going to be enriched by the more complete and powerful MDC tool developed by the UNISS.

The OODK is used in the context of UC5-D1 to instantiate the Onboard Overlay Compute Platform that is used as a fabric for the AES Hardware Accelerator generated with the Multi-Dataflow Compose tool designed by UNISS (see Figure 81).

The UC5-D1 application providers designed an HW accelerator for the AES cryptographical encryption using MDC. The generated dataflow graph (DF Network) is then integrated into the Onboard Overlay Compute Platform using the OODK scripts. The OODK is also used to synthesize the whole RTL design into a Xilinx FPGA bitstream and implement the high-level programming interface for the AES accelerator through the OpenMP 4.0 Spec. Figure 83 shows the dependency/interoperability between OODK and the MDC inside the UC5-D1.

Current Status

OODK has been evaluated with the Onboard Overlay design methodology developed in WP3, providing end-to-end examples of HWPU accelerators under development within the WP4 effort. Note: OODK has not been validated in UC5-D1 directly because the proposed tools and runtime libraries are not "visible" at the UAV-user level but only on the engineering side.

OODK is used for implementing and designing software Subsystem and Component elements of the C4D Drone Reference Platform targeting the Onboard Overlay Compute Platform (WP3-22).

OODK is used in UC5-D1 for software (application) design and implementation and for implementing HW (FPGA-Overlay) design and integration.

completed: - Enabling OpenMP4 offloading support, OODK enables easy and streamlined computation offload between host and HW Application-Specific Accelerators: single source and compiler-assisted code generation (pragma). Comparison with synthetic and realist applications (see WP4) shows a minor implementation effort regarding LOC written for the application. - OODK enables automatic integration of HW Application-Specific Accelerators with a single configuration file (python). Users can integrate accelerators without writing in HDL and without the need to be an expert HW designer. Comparison with synthetic and realist applications (see WP4) shows a minor implementation effort in terms of LOC written for the HW integration and design time.

Design and Implementation

The snipped above shows the only configuration file for OODK that the user should compile to integrate one or more HW Application-Specific Accelerators. For the application design, our tool provides a single-source OpenMP4.5-enabled programming interface. Supporting an OpenMP4.5 Accelerator Model means having an OpenMP4.5-enabled compiler supporting both the host ISA and the RISC-V ISA and a runtime system implementing the OpenMP standard. Thus, the OODK collection contains:  Clang/LLVM Compiler. Compiler configured for supporting OpenMP offloading from AARCH64 ISA to RISC-V ISA.  Overlay Runtime Libraries. Host and Overlay Communication and Runtime Libraries.  Overlay Rootfs and Linux OS Generator. Automated scripts for the creation of Linux-based rootfs for the host.